Direct current to direct current (DC/DC) converters generally include an upper driver portion and a lower driver portion to deliver current to a load via an external inductor and an external capacitor.
For example, FIG. 1 shows a DC/DC converter system 100 in a step-down configuration known as a “buck” configuration. A pulse width modulator (PWM) controller 110 controls an upper driver incorporating a PMOS transistor 120 and a lower driver incorporating an NMOS transistor 130. Transistors 120 and 130 are commonly implemented using power transistors. A load 140 may be coupled with the output of transistor 120 and transistor 130 via an inductor 150 and a capacitor 160. System 100 also includes parasitic inductances L1 and L2, which may be caused by the inductance of the packaging, printed circuit board traces, finite equivalent series inductance (ESL) of an external decoupling capacitor such as capacitor 180, or other factors. In operation, PWM controller 110 turns transistor 120 and transistor 130 on and off alternately, so current flows through current path I1, and current path I2 alternately.
The configuration shown in FIG. 1 may not be optimal for high current applications, since PMOS power transistors generally have a relatively large on-state drain/source resistance RDS-on. For example, RDS-on for a PMOS power transistor is generally about two to three times higher than the RDS-on value of a comparably sized NMOS power transistor. To achieve a comparable value of RDS-on, the size of the PMOS power transistor would need to be increased. However, larger devices experience an increased gate switching loss and may lead to undesirably large die sizes.
Alternately, NMOS power transistors may be used for both the upper and lower drivers. FIG. 2A shows such an alternate implementation. A DC/DC converter system 200 includes a PWM controller 210 to control an upper driver including a top NMOS transistor 220 and a bottom NMOS transistor 230. System 200 also includes a bootstrap pre-driver 215 and a bootstrap capacitance CBS 218 in communication with top transistor 220.
Because of the lower value of RDS-on for NMOS transistors relative to comparable PMOS transistors, the implementation shown in FIG. 2A may provide higher efficiency performance than the implementation of FIG. 1. However, the addition of the bootstrap pre-driver increases the complexity of the system. If NMOS transistor 220 is integrated, the on-state breakdown voltage of NMOS transistor 220 may be too low for higher current applications, or the reliable input voltage operating range may have to be decreased.
For example, FIG. 2B shows typical 5V NMOS transistor breakdown and snap back behavior for a number of values of VGS. In contrast, FIG. 2C shows typical 5V PMOS transistor breakdown behavior for the same values of VGS. An NMOS transistor can handle large VDS when its gate voltage is low or the transistor is off. As FIG. 2C illustrates, PMOS transistors are typically better able to handle on-state stress than comparable NMOS transistors.